The present invention relates to memory usage and management, and more particularly, to efficient use of cache memory using an expiration timer.
Cache memory is a small and extremely fast storage construct that is not available for use by software or other applications, as it is completely managed by hardware. Cache memory is used to store the most recently used (MRU) main memory (MM) data, otherwise known as working memory data. Cache memory is used in a wide variety of microprocessors, micro processing units (MPUs), central processing units (CPUs), multi-core processors, and other processors and processing units that are expected to provide faster, more efficient processing of MRU MM data.
Some more recently released MPUs, such as a PowerPC, are provided with a memory called an L1 cache that is utilized for executing loading and storing instructions (e.g., “Load/Store” instruction) at higher speeds than are possible using traditional memory systems. The addresses in which a “Load” or a “Store” instruction are usually performed in executing a program by the MPU are typically located close to one another, on a short-term basis. To take advantage of this typical address location, L1 cache is configured to store consecutive bytes numbering in the tens to hundreds, which is used to complete processing of a received instruction inside the MPU at higher speeds than are otherwise possible using memory stored outside of the MPU. However, the capacity of the L1 cache is much smaller than the capacities of any of a L2 cache, a L3 cache, a L4 cache, or a main memory outside the MPU. Furthermore, when an access to perform a “Load/Store” is made to an address for data other than data existing in the L1 cache, an operation is performed in which data in the L1 cache is written down to a memory outside the MPU and a new data block is called into the L1 cache.
During this operation, corruption of data may occur in rare cases, and may be caused due to the MPU not using updated data from the main memory, but rather using outdated data in the L1 cache by mistake.